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Category: Computer system architecture by morris mano chapter 12 ppt

Computer system architecture by morris mano chapter 12 ppt

Arithmetic Processor Arithmetic instruction in digital computers manipulate data to produce results necessary for the solution of the computational problems. An arithmetic processor is the part of a processor unit that execute arithmetic instruction An arithmetic instruction may specify binary or decimal data, and it may be represented in, Fixed point integer or fraction OR floating point form.

An arithmetic processor is simple for binary fixed point add instruction It would be more complicated if it includes all arithmetic operations for binary and decimal data in both representations. How to perform basic arithmetic operation with signed magnitude require valuable knowledge for its hardware implementation. The designer must be thoroughly familiar with sequence of steps in order to carry out the operation and achieve a correct result. Algorithm: The solution to any problem that is stated by a finite number of well defined procedural step is called algorithm.

Flowchart: The convenient method for presenting algorithm is a flowchart. The computational steps are specified in rectangular boxes Decision steps indicated inside diamond-shaped boxes from which two or more alternate path emerge. Addition and Subtraction Data types considered for the arithmetic operations are, Fixed-point binary data in signed magnitude representation Fixed-point binary data in signed-2s compliment representation Floating point binary data Binary coded decimal BCD data Negative fixed point binary number can be represented in three ways, Signed magnitude most computers use for floating point operations Signed 1s compliment Signed 2s compliment most computer use for integers.

Addition and Subtraction with SignedMagnitude Data Eight different conditions to consider for addition and subtraction. Addition Subtraction algorithm: When the signs of A and B are identical differentadd the two magnitudes and attach the sign of A to the result. When the sign of A and B are different identicalcompare the magnitudes and subtract the smaller number from the larger.

For equal magnitude subtract B from A and make the sign of the result. Parallel subtractor are needed to perform A B or B A. Can be accomplished by means of compliment and add. The sign relationship can be determine from an exclusive-OR gate with As and Bs as inputs Output carry are transferred to E flip-flop Where it can be checked to determine the relative magnitude of the Nos. Multiplication Algorithm Multiplication of two fixed point binary numbers in signed magnitude representation is done by the process of successive shift and add operations.

Numerical Example:. The process consist of looking at successive bits of the multiplier, least significant bit first. If the multiplier bit is 1, multiplicand is copied down otherwise zeros are copied down Copied number in successive line shifted one position to the left from the previous number. Finally, the numbers are added and their sum forms the product. Hardware Implementation Multiplication process is change slightly. First, instead of providing registers to store and add simultaneously as many binary numbers as there are bits in multiplier, It is convenient to provide an adder for the summation of two number And successively accumulate the partial products in a register.

Second, instead of shifting the multiplicand to the left, the partial product is shifted right Which result in leaving the partial product and the multiplicand in the required relative position.

Third, when the corresponding bit of the multiplier is 0, there is no need to add all zeros to the partial product since it will not alter its value. The hardware for multiplication consist of the equipment shown in figure. The multiplier stored in Q register and its sign in Qs. The sequence counter SC is initially set to a number equal to the number of bits in the multiplier.

The counter is decremented by 1 after forming each partial product. Fig: Hardware for multiply operation. Initially the multiplicand is in register B and the multiplier in Q. The sum of A and B forms a partial product which is transferred to the EA register. Both the partial product and multiplier are shifted to the right. After the shift, one bit of partial product is shifted into Q, pushing the multiplier bit one position to the right.

In this manner, the rightmost flip-flop in register Q, designated by Qn, will hold the bit of the multiplier, which must be inspected next. Learn more about Scribd Membership Home. Read free for days Sign In. Much more than documents. Discover everything Scribd has to offer, including books and audiobooks from major publishers. Start Free Trial Cancel anytime.Slideshare uses cookies to improve functionality and performance, and to provide you with relevant advertising.

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Gladson Rashila. Bala Ganesh. No Downloads. Views Total views.It is made up of nerve cells, called neurons, and supporting cells called glial cells. It is purely a dynamic structure, where the content gets upgraded according to the evaluation done by the users. A basic Flip-Flop circuit can be constructed in two ways. This Book provides an clear examples on each and every topics. MCHP is a leading provider of microcontroller, mixed-signal, analog and Flash-IP solutions, providing low-risk product development, lower total system cost and faster time to market for thousands of diverse customer applications worldwide.

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Computer System Architecture By Morris Mano Chapter 12 Ppt

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